1. Field of the Invention
The present invention relates generally to the field of memory technology, and more particularly, to a 4F2 memory cell having a circle-segment-shaped buried bit line and a vertical transistor above the buried bit line. The present invention further provides a method for fabricating the novel buried bit line structure and the vertical transistor.
2. Description of the Prior Art
In order to accelerate operating speed of integrated circuits and to meet customers' demands for miniaturizing electronic devices, physical dimensions of transistors in a semiconductor apparatus are continuously reduced. With the reduction in physical dimensions of transistors, the length of channel regions in the transistors is reduced as well. Thus, a severe short channel effect would occur in the transistors, and its ON current is likely to decrease.
A conventional solution to this issue is to enhance the dopant concentration in the channel region. However, this method causes an increased leakage current and therefore affects the reliability of devices. Another approach is to use a vertical transistor structure. For example, the vertical transistor structure is formed in the deep trench of the substrate so the operating speed and integration of integrated circuits are enhanced and short channel effect can be alleviated. Currently, improvements in structural design and channel control of the existing vertical transistors are studied aggressively in this field.